The present invention relates to performing a change order during, or after, a chip is designed, and more specifically, to using a Boolean equivalence checking tool to perform the change order.
In chip design, an engineering change order is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic layout tool. Before the chip masks are made, engineering change orders (ECOs) are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place, route, layout extraction, and timing verification. Electronic design automation (EDA) tools are often built with incremental modes of operation to facilitate this type of ECO.
One of the most common ECOs in ASIC design is the gate-level netlist ECO. In this flow, engineers manually (and often tediously) edit the gate-level netlist, instead of re-running logic synthesis. The netlist files are searched for the logic affected by the change, edited to implement the changes, and verified to ensure changes are made without introducing errors into the design. This is a very time and resource-intensive process highly subject to errors. Therefore, formal equivalence checking is normally used after ECOs to ensure the revised implementation matches the revised specification.